FEATURES
32 way Asynchronous Packet Switch
32 x 100 Mbits/s serial bi-directional links
300 Mbytes/s bandwidth
High rate of packet processing -up to 200 Mpackets/s
Less than 1 us packet latency
Wormhole interval routing algorithm: routes packets of any length
Grouped adaptive routing
Non-biocking crossbar
Concurrent processing of packets
Partitionable architecture
Cascadable to any depth
Support for hierarchical routing
Supports 2-phase routing: hot spot avoidance
Separate control system
No loss of signal integrity
Full flow-control
Bit and packet level error handling
Uses 4 wire per link Data-Strobe encoding for simple clock extraction-eliminates need for high speed clocks
On-board phase locked loop requires single 5MHz crystal input
On-chip buffering of 70 tokens per link
Highly configurable:28Kbits user-programmed data
Boundary scan support
Available in 208 CLCC package